1. Field of the Invention
The present invention relates to a method for forming semiconductor devices, and more particularly to a method for forming high voltage devices compatible with low voltage devices on a semiconductor substrate.
2. Description of the Prior Art
Recently, the demand for semiconductor devices has rapidly increasing due to the usage of a large number of electronic devices. The integrated circuits for computer peripherals, such as output/input circuits or watcher circuits, require a controlling circuit and a driving circuit. In general, low voltage devices are utilized in the controlling circuit, while high voltage devices are utilized in the driving circuit. However, the high/low voltage-integrated devices are also utilized in many other devices, such as an LCD display for a notebook, electronic parts for a watch etc., except for the computer peripherals. Therefore, it is frequent to utilize high/low voltage-integrated devices in semiconductor devices.
FIG. 1A to FIG. 1C show cross-sectional views respectively for various steps of the method for forming a conventional high voltage device according to the current deep-submicron technique. In FIG. 1A, firstly, N wells 102 and 104 are formed in the substrate 100 through an N well blank implantation. The N wells 102 and 104 are generally formed by an N type ion implantation, for example, phosphorus or arsenic ion implantation. In FIG. 1B, subsequently, a well compensation process is performed to compensate the N well 102 to a P well 106 for an NMOS transistor in the substrate 100. The well compensation process is performed, utilizing a P type ion implantation, for example, boron ion implantation. For the N type ion implantation, phosphorus or arsenic ion prefers closing to the surface of the N well. While, for the P type ion implantation, boron ion prefers far away from the surface of the P well. Hence, well compensation for the N well 102 compensated to the P well 106 would result in non-uniform concentration distribution for the P well 106. An additional well compensation is required.
In FIG. 1C, a gate oxide layer 108 and a polysilicon gate 110 are formed on the substrate 100, prior to forming N.sup.- type doped regions 112a and 112b. Since the N-grade implantation to form N.sup.- type doped regions 112a and 112b is subsequent to the formation of the polysilicon gate 110, the N.sup.- type doped regions 112a and 112b are subject to only one thermal cycle, e.g. an annealing process. Thus, the diffusion depth of the N.sup.- type doped regions 112a and 112b is shallow. Moreover, as described in the above, the doped concentration of the compensated P well 106 is not uniform, due to the previous N well blank implantation. Hence, it is difficult to obtain a good doping profile for the snap-back voltage, and therefore, the hot carrier effect is not easily controlled.
Accordingly, it is an intention to find out a method for forming high/low voltage-integrated device to overcome the drawbacks of the conventional device.
It is one object of the present invention to provide a method for forming high voltage devices compatible with low voltage devices on a semiconductor substrate, in which a single N well and P well are formed as wells sufficient for a respective high voltage device and a respective low voltage device. Hence, it is not required for well compensation, and the number of masks for ion implantation is decreased.
It is another object of the present invention to provide a method for forming high voltage devices compatible with low voltage devices on a semiconductor substrate, in which an N-grade implantation is performed to form N.sup.- type doped regions in a P well, prior to a gate oxide layer and a polysilicon gate formation. By this method a better doping profile for the snap-back voltage is obtained and the breakdown voltage is increased.